The present invention relates to imaging processing apparatus for effecting signal processing of image signals outputted from an imaging device, and more particularly relates to an imaging processing apparatus for effecting such imaging adjustments as automatic exposure adjustment and white balance adjustment.
Those imaging apparatus such as digital cameras where imaging signals obtained by using an imaging device, such as CCD or CMOS are converted into digital signals and are then subjected to signal processing are generally provided with functions for effecting for example automatic exposure control (hereinafter abbreviated as AE), automatic focus control (hereinafter abbreviated as AF), and automatic white balance adjustment (hereinafter abbreviated as AWB) for the obtained imaging signals so that the photographer can take pictures under an optimum condition.
In the above described imaging processing of the imaging apparatus, predetermined regions of an imaging frame are respectively set as photometric area and focus area to detect the imaging signals in the regions. Based on the result of such detection, the imaging apparatus is then adjusted to an optimum condition in taking images. For example, AE control is to obtain and effect an optimum exposure amount with setting diaphragm or the like based on an evaluation value obtained by integrating output color signal components of the imaging device, and AWB control is to correct color balance by correlating the respective colors based on an evaluation value as described.
An imaging processing apparatus of the construction as will be shown in the following has been proposed for example in Japanese Patent Application Laid-Open Hei-11-239291 as the imaging processing apparatus using a technique for achieving the above described control. FIG. 1 is a block diagram showing construction of the imaging processing apparatus as disclosed in the publication. Referring to FIG. 1, an imaging section 101 includes an optical unit comprised for example of lens and solid-state imaging device, a drive circuit for driving the solid-state imaging device, and a drive mechanism for moving lens and diaphragm to a predetermined position. A drive section 102 is a means for generating for example drive signals for adjusting the aperture of diaphragm and drive signals for driving the solid-state imaging device. An analog signal processing section 103 is a means for clamping and amplifying imaging signals outputted from the imaging section 101 to output them as image signals. An A/D conversion processing section 104 is for converting the image signals consisting of analog signals into digital signals, and a digital signal processing section 105 is for effecting for example γ processing on the digital image signals.
A recording/reproduction processing section 106 is to record the image signals for example into a memory card and to effect reproduction thereof. D/A conversion processing section 107 is a means for converting digital signals into analog signals to provide a visible displaying thereof-on a monitor 109 of display section 108. Numeral 111 denotes a control section such as of CPU and 112 denotes operating switches. AF integration block 113 is a means for computing an AF evaluation value. A common integration block 114 is a means for computing an evaluation value for use in AE/AWB control and, in some modes, an evaluation value for effecting AF, internally including an integrating section for dividing an image into a plurality of blocks to integrate an evaluation value and a memory for retaining the result of the integration.
An operation of thus constructed imaging processing apparatus will now be described. The imaging signals obtained from the imaging section 101 go through the analog signal processing section 103, are converted into digital signals by the A/D conversion processing section 104, and are inputted into the digital signal processing section 105. The image signals from the digital signal processing section 105 are recorded into a memory card through the recording/reproduction processing section 106 or displayed on the monitor 109 of display section 108 according to an instruction given from the operation switches 112. Further, the image signals from the A/D conversion section 104 are inputted also into the AF integration block 113 and common integration block 114. At the common integration block 114, the inputted image is divided into a plurality of blocks, and is integrated block by block to generate an evaluation value. The generated evaluation value is transferred for example through an internal bus to the control section 111 where control signals to the drive section 102 are generated.
FIG. 2 is a block diagram showing construction of the common integration block 114. Further, FIG. 3 is a timing chart for explaining operation of the common integration block 114. Referring to FIG. 2, a high luminance suppressing section 201 is a circuit for effecting for example knee processing on the output of the A/D conversion processing section 104 of FIG. 1. Inputted respectively to the input of an input data switching section 202 are the result of the processing at the high luminance suppressing section 201, and integration results AFa, AFb of the AF integration block 113 of FIG. 1. The input data switching section 202 switches from operation of each evaluation value to another at each field so as to make desired operation possible in such a manner as shown in FIG. 3 that AE/AWB integration for example is effected in a first field and AF integration in a second. A register setting section 203 is to set an area to be integrated. An evaluation value computing section 204 effects integration processing and retains values in the course of the integration and an integration result to an integration memory 205. Further, operation results (evaluation value) at the evaluation value computing section 204 are read out to the control section 111 when operation of each field is completed. The control section 111 then generates control signals for AE/AWB processing based on the evaluation values obtained by computation.